The present invention relates to MIS transistors (metal-insulator-semiconductor) and in particular MOS transistors (metal-oxide-semiconductor) and more specifically a process for the production of a MIS transistor with a raised substrate/gate dielectric interface end.
It is applicable to the production of submicron MOS transistors (whose dimensions do not exceed approximately 1 micrometer) and therefore to the production of integrated circuits resulting from very large scale integration (VLSI).
Very large scale integration of MOS transistors makes it necessary to reduce the dimensions of these transistors and particularly the length of their channels. However, the reduction of the length of the channel of a MOS transistor causes aging problems with respect thereto. Thus, the transistor deteriorates over a period of time and this is more pronounced as the channel length decreases and particularly when it operates in the saturation state, due to electrons in the channel brought into a very high energy form by intense electric fields produced in the channel close to the drain of the transistor (assumed to be a N channel), said electrons being called "hot electrons" and cause transistor deterioration. Thus, these electrons are injected into the gate dielectric and disturb the operation of the transistor. As the channel length decreases, the electric fields become more intense.
In the same way, a P channel MOS transistor deteriorates during time due to the holes in the channel (said holes in this case constituting the minority carriers), which are brought into a very high energy state by intense electric fields close to the transistor drain, when the transistor operates in the saturation state.
Various methods have already been proposed for solving these problems. One of the most widely used methods is the LDD or lightly doped drain method, which is in particular referred to in the article by S. Bampi et al, published in IEDM 85, 9.2, IEEE, 1985, pp. 234 to 237.
FIG. 1 diagrammatically illustrates the LDD method. In a MOS transistor having a substrate 2, a gate 4 separated from the substrate by a dielectric layer 6 having a planar interface with the substrate 2, as well as a source 8 and a drain 10 having portions extending beneath said interface, portion 12 corresponding to the drain 10 is only lightly doped compared with the remainder of the drain.
LDD reduces the maximum value of the electric field close to the drain. However, it introduces an electric resistance in series with the transistor channel, which is prejudicial to the transformer performance characteristics.
Other known methods, optionally combined with the LDD method, make it possible to pass the electron current (assuming that it is a N channel MOS transistor) in depth close to the drain, in such a way that the "hot electrons" are produced remote from the substrate/dielectric interface, where they can be trapped. A depth increase of 10 nanometers of the electron current makes it possible to bring about a ten times less rapid deterioration of the dielectric.
An example of these other methods is also given in the aforementioned article and is diagrammatically illustrated in FIG. 2. In the MOS transistor shown, substrate 2 is e.g. of the P.sup.- type and, beneath the planar dielectric/substrate interface is located a type P zone 14 connecting source 8 to drain 10. Beneath said interface, the drain 10 comprises, starting from zone 14, a type N.sup.- portion 16 and a type N.sup.+ portion 18 and a type P.sup.+ zone 20 between said portions 16 and 18.
However, the MOS transistor diagrammatically shown in FIG. 2 suffers from the disadvantage of it being difficult to reduce its size (while obviously maintaining its proportions), because in particular it is difficult to produce a small zone 20.